Exemplary embodiments relate generally to the patterns of a nonvolatile memory device and a method of forming the same and, more particularly, to the patterns of a nonvolatile memory device and a method of forming the same, which are capable of improving the failure rate of the device.
In line with an increase in the degree of integration of nonvolatile memory devices and a reduction of the pitch between memory cells, the proportion of defective devices produced in a process of forming patterns constituting a nonvolatile memory device has increased. In particular, a NAND flash memory device having a structure advantageous to a high degree of integration is increasingly likely to have failures in a process of forming gate patterns.
FIGS. 1, 2A, 2B, and 2C are diagrams illustrating a known method of forming the patterns of a nonvolatile memory device. In particular, FIGS. 1 and 2 depict a method of forming the gate patterns of a NAND flash memory device. FIGS. 2A, 2B, and 2C are cross-sectional views taken along lines I-I′, II-II′, and III-III′, respectively, in FIG. 1.
Referring to FIG. 1, and FIGS. 2A, 2B, and 2C a tunnel insulating layer 3 and a charge trap layer 5 are stacked over a semiconductor substrate 1. The charge trap layer 5 and the tunnel insulating layer 3 are etched so that the semiconductor substrate 1 is exposed in the longitudinal direction. Next, trenches 7 are formed in the semiconductor substrate 1 in a longitudinal direction by etching the exposed semiconductor substrate 1. Although not shown, the process of etching the charge trap layer 5 and the tunnel insulating layer 3 and the process of etching the exposed semiconductor substrate 1 may be performed by using isolation hard mask patterns, formed on the charge trap layer 5, as an etch mask before the charge trap layer 5 is formed. The isolation hard mask patterns may be removed after the trenches 7 are formed.
After the trenches 7 are formed, the trenches 7 are filled with isolation insulation layers 9. Isolation structures, including the trenches 7 and the isolation insulation layers 9 and electrically isolating memory cells, are formed. An active region A is defined between the isolation structures in the longitudinal direction. The tunnel insulating layer 3 and the charge trap layer 5 may remain only over the active regions A.
Next, the height of the isolation insulation layer 9 is lowered by etching the isolation insulation layers 9 to control the Effective Field oxide Height (EFH) of the isolation structure. The EFH of the isolation structure is preferably lower than the height of the charge trap layer 5 such that the area in which the charge trap layer 5 and a control gate layer 13, forming a gate pattern, come into contact with each other is increased and thus the coupling ratio between the charge trap layer 5 and the control gate layer 13, forming the gate pattern, can be improved. Furthermore, the EFH of the isolation structure is preferably higher than the height of the tunnel insulating layer 3 to prevent the occurrence of a leakage current because the active regions A of the semiconductor substrate 1 are exposed. If the EFH is controlled as described above, the sidewall of the charge trap layer 5 is exposed.
Next, a dielectric layer 11 is formed on the isolation insulation layer 9 and the exposed surface of the charge trap layer 5. Next, the control gate layer 13 of a thickness enough to fill the space between the charge trap layers 5 is formed on the dielectric layer 11. Next, a gate hard mask pattern 15 is formed on the control gate layer 13.
The gate hard mask pattern 15 comprises a plurality of patterns separated in parallel, which is formed to cross the isolation structures and the active regions A. The control gate layer 13, the dielectric layer 11, and the charge trap layers 5 are etched using the gate hard mask pattern 15 as an etch mask to pattern the control gate layer 13, the dielectric layer 11, and the charge trap layers 5. Accordingly, as shown in FIG. 2, gate patterns G in each of which the control gate layer 13, the dielectric layer 11, and the charge trap layer 5 are stacked are formed in respective regions in which the gate hard mask pattern 15 and the active region A cross each other. Meanwhile, the control gate layers 13 of the gate patterns G are connected in the lateral direction to cross the active regions A, thus becoming word lines.
The device can be properly driven when the control gate layer 13, the dielectric layer 11, and the charge trap layer 5 not overlapping the gate hard mask patterns 15 are fully removed in the process of patterning the control gate layer 13, the dielectric layer 11, and the charge trap layer 5 using the gate hard mask pattern 15 as the etch mask. However, the dielectric layer 11, formed on the sidewall of the charge trap layer 5 and over the isolation structure having a controlled EFH, is not fully removed, so that a dielectric fence 11a is formed. The dielectric fence 11a provides a charge transfer path, thus causing a bridge between the gate patterns G that should be electrically insulated. To prevent the dielectric fence 11a from being formed, the dielectric layer 11 may be excessively etched by using the gate hard mask pattern 15 as an etch mask. In this case, however, the isolation insulation layers 9 are excessively etched, and thus the EFH of the isolation structure may be lost.
The dielectric fence 11a causes not only a bridge between the gate patterns G, but also the deterioration of a cycling characteristic of the device. The loss of the EFH causes reduction in reliability of the device. Furthermore, the dielectric fence 11a, together with the gate hard mask pattern 15, serves as an etch mask to prevent the charge trap layer 5 below the dielectric fence 11a from being removed, thereby causing failure of the gate patterns G.